The present invention relates to a semiconductor device having a multilevel interconnection structure and a method of manufacturing the same.
The multilevel interconnection technique is used to integrate semiconductor integrated circuits at a higher density. In this multilevel interconnection technique, a wiring layer must be formed on a flatter insulating layer. As a scheme of obtaining such a flat insulating layer, chemical and mechanical polishing (CMP) is available.
For example, when a two-level interconnection structure is to be formed, an interlevel insulating film is formed after the first electrode wiring layer is formed, and the second electrode wiring layer is formed on the interlevel insulating film. The surface of the interlevel insulating film is not flat since a step is formed on it due to the presence of the first electrode wiring layer. Accordingly, the surface of the interlevel insulating film may be planarized by CMP described above, and the second electrode wiring layer may be formed on the planarized interlevel insulating film.
An electrode wiring layer is formed by photolithography, etching, and the like. In photolithography, a foreign matter produced by resist peeling on the peripheral portion of a wafer causes a decrease in yield of the manufacture of semiconductor devices and poses a problem accordingly.
Resist peeling will be briefly explained. In the manufacture of semiconductor integrated circuits, a pattern is formed by photolithography on a photoresist formed on the wafer by coating, and an underlying metal material is etched by using the formed pattern as a mask, thereby forming an electrode wiring layer.
During this etching, the wafer is held in an etching apparatus by clamping the peripheral portion of the wafer with a clamp. More specifically, when processing a wafer coated with a resist, the clamp and the resist film on the peripheral portion of the wafer come into contact with each other on the periphery of the wafer. When the clamp comes into contact with the resist film in this manner, the resist film on the peripheral portion of the wafer peels off to produce a foreign matter.
The wafer is conveyed or temporarily kept in stock as it is stored in a wafer carrier. In this case as well, the resist on the peripheral portion of the wafer peels off as it comes into contact with the wafer carrier, and produces a foreign matter.
In this manner, the presence of the resist film on the peripheral portion of the wafer produces a foreign matter to decrease the yield in the manufacture of semiconductor devices. Even if the resist film on the peripheral portion of the wafer does not peel off but remains until the separation step, it does not contribute at all to improvement in yield of the semiconductor devices.
As described above, the resist film on the peripheral portion of the wafer in photolithography merely causes a decrease in yield and is accordingly removed by the following method or the like prior to etching.
For example, in photolithography of a positive resist, the peripheral portion of the wafer is exposed before development and, during development, the resist on the peripheral portion of the wafer is removed by development. In this case, since the resist is removed from the peripheral portion of the wafer, a layer under the resist, e.g., a metal film under the resist, is also removed from the peripheral portion of the wafer in the following etching step.
In a normal semiconductor device manufacturing process, since photolithography and etching are repeated 10 times or more, removal of the resist from the peripheral portion of the wafer is performed each time photolithography and etching are performed. This removal of the resist film is performed for the purpose of forming a through hole not only in an electrode wiring layer but also in an interlevel insulating film. Therefore, the electrode wiring layer or the interlevel insulating film as the etching target is removed from the peripheral portion of the wafer.
Assume that the first to third layers are to be sequentially formed on a wafer. Also assume that the outermost peripheral end of the second layer is located inside the outermost peripheral end of the first layer on the peripheral portion of the first layer, i.e., a case wherein the outermost peripheral end surface of the first layer is exposed on the peripheral portion of the wafer.
If a resist film removal region of the third layer on the peripheral portion of the wafer is located outside the outermost peripheral end of the second layer, the outermost peripheral end of the third layer becomes outside the outermost peripheral end of the second layer accordingly. Hence, on the outermost peripheral end of the peripheral portion of the wafer, the first and third layers are undesirably in contact with each other.
In this state, if the adhesion properties between the first and third layers are poor, the end of the third layer peels off from the first layer on the peripheral portion of the wafer to produce a foreign matter. If the first and third layers form an electrode wiring layer, a leakage current flows between them.
FIG. 3 shows a conventional semiconductor device of Japanese Patent Laid-Open No. 8-31710 free from this problem. A first interlevel insulating film 2, an electrode wiring layer 3, and a second interlevel insulating film 4 are sequentially formed on a silicon substrate 1. Referring to FIG. 3, a resist film removal region in photolithography is designed such that the outermost peripheral end, on the peripheral portion of the wafer, of a layer which is formed later is located more inside.
In the conventional semiconductor device shown in FIG. 3, since the end of the electrode wiring layer 3 is exposed from the peripheral portion of the wafer, if the surface of the second interlevel insulating film 4 is polished by CMP, the second interlevel insulating film 4 is undesirably ground to produce chippings. These chippings may enter the polish surface to damage it.
Even when the electrode wiring layer 3 is not formed on the outermost peripheral end of the peripheral portion of the wafer but is covered with the second interlevel insulating film 4, the closer to the edge of the wafer, the smaller the thickness on the peripheral portion of the wafer. In particular, the lower among three or more layers, the smaller the thickness of its end.
For this reason, if the second interlevel insulating film 4 on the electrode wiring layer 3 is polished by CMP, the second interlevel insulating film 4 on the peripheral portion of the wafer, which has become thin, is further ground to disappear. Then, the end of the electrode wiring layer 3 is exposed. In this case, when CMP is continued, the exposed electrode wiring layer 3 is ground, and its chippings enter the polish surface of the interlevel insulating film to damage it.